CAN-Based Aging Monitoring Technique for Automotive ASICs With Efficient Soft Error Resilience

Built-in Soft Error Resilience Structures

This article describes a new paradigm in the design of soft error resilient architectures involving reuse of on-chip resources for multiple functions at various stages of manufacturing and field use. For example, on-chip Design for Testability resources for scan can be reused for soft error protection during normal operation. We focus on the sequential elements (flip-flops and latches) of a des...

Soft Error Resilience of Probabilistic Inference Applications

With shrinking device size and increasing complexity, soft errors are becoming an issue in the reliability of digital systems. To make efficient robust systems, it is important to understand how soft errors affect the quality of output for the target applications. Probabilistic inference applications are interesting since they produce non-exact results and yet are useful in many different field...

Generating Control Logic for Optimized Soft Error Resilience

Aggressive technology scaling has necessitated the development of techniques to ensure resilience to device faults, including soft errors, circuit wear-out, variability, and environmental effects. All error resilience techniques employ some form of redundancy, resulting in added cost such as area or power overhead. Existing selective hardening techniques have been focused on identifying on the ...

How Can Usage Monitoring Improve Resilience?

Fault Injection Verification of IBM POWER6 Soft Error Resilience

Full chip statistical fault injection has been performed on a hardware emulated POWER6 platform. These results were validated against proton beam injection results. The fault isolation, error recovery and error logging capabilities of the POWER6 enabled measurement of the architectural derating factors. The proportion of errors as well as derating factors matched well between the simulated and ...